Integrated circuits (ICs), the key components in thousands of electronic systems, generally include interconnected networks of electrical components fabricated on a common foundation, or substrate. Metal structures are commonly used to electrically connect semiconductor features, such as capacitors or transistors, or to define a specific IC, such as a computer memory or microprocessor. The deposition and processing methods used to form the metal structures may affect the quality of the metal structures and impact overall manufacturability, performance, and lifetime of the IC. Thus, the methods used to form the metal structures are increasingly determining the limits in performance, density and reliability of integrated circuits.
As a non-limiting example, the deposition and processing methods used to form active electrodes for memory cells of conductive bridging random access memory (CBRAM) devices may greatly affect the performance and reliability of such devices. Memory cells of CBRAM devices conventionally utilize metallic or ionic forms of silver (Ag) or copper (Cu) to form a conductive bridge between an inert electrode and an active electrode. The active electrode serves as the source of the Ag or Cu. The conductive bridge is formed by the drift (e.g., diffusion) of Ag or Cu cations (by application of a voltage across the electrodes) from the active electrode, through an active material of the memory cell, and to the inert electrode, where the Ag or Cu ions are electro-chemically reduced. The conductive bridge may be removed (by applying a voltage with reversed polarity across the electrodes) or may remain in place indefinitely without needing to be electrically refreshed or rewritten.
A problem with the fabrication of CBRAM devices arises due to the difficulty of processing the Ag or Cu. For example, Cu cannot be etched with conventional RIE techniques, and is typically processed in a damascene flow. Also, there are currently no chemical vapor deposition (CVD) or atomic layer deposition (ALD) techniques for Ag. In addition, the ability to deposit Cu and Ag in small openings is limited. Therefore, deposition is conventionally conducted by physical vapor deposition (PVD), which limits the scalability of Ag damascene flows. It is, therefore, currently of interest to minimize the extent of Ag or Cu processing during the integration and fabrication of semiconductor devices, such as CBRAM devices.
Selective deposition techniques are one way of minimizing Ag or Cu processing. In such techniques, pre-patterned chemical specificity enables materials, such as Ag or Cu, to be preferentially deposited only in desired locations, which avoid the need to etch or polish such materials. Electroless plating is a conventional selective deposition technique. However, electroless plating exhibits variability in nucleation and growth rates, which may disadvantageously result in inconsistencies in the volume of metal deposited at each site within a memory array, significantly impacting operations where the quantity of selectively deposited metal must be critically controlled. Electroless plating also requires substrates that are electrochemically active, whereas, in certain semiconductor devices (e.g., MOS devices, MIM devices, and CBRAM devices), it is desirable to selectively deposit materials to substrates that are electrochemically inactive (e.g., dielectric materials). Accordingly, improved methods of forming metal structures for semiconductor devices (e.g., CBRAM devices) using selective deposition techniques are desired, as are related methods of forming memory cells.